Flash and other types of electronic memory devices are constructed of thousands or millions of memory cells, adapted to individually store and provide access to data. A typical memory cell stores a single binary piece of information referred to as a bit, which has one of two possible states. More recently, dual bit memory cell architectures have been introduced, wherein each cell can store two bits of data. The cells are commonly organized into multiple cell units such as bytes which comprise eight cells, and words which may include sixteen or more such cells, usually configured in multiples of eight. Storage of data in such memory device architectures is performed by writing to a particular set of memory cells, sometimes referred to as programming the cells. Retrieval of data from the cells is accomplished in a read operation. In addition to programming and read operations, groups of cells in a memory device may be erased, wherein each cell in the group is programmed to a known state.
The individual cells are organized into individually addressable units or groups such as bytes or words, which are accessed for read, program, or erase operations through address decoding circuitry, whereby such operations may be performed on the cells within a specific byte or word. The individual memory cells typically include a semiconductor structure adapted for storing a bit of data. For instance, many conventional memory cells include a metal oxide semiconductor (MOS) device, such as a transistor in which a binary piece of information may be retained in the form of electrical charge. The memory device includes appropriate decoding and group selection circuitry to address such bytes or words, as well as circuitry to provide voltages to the cells being operated on in order to achieve the desired operation.
The erase, program, and read operations are commonly performed by application of appropriate voltages to certain terminals of the cell. In an erase or program operation the voltages are applied so as to cause a change in charge to be stored in the memory cell. In a read operation, appropriate voltages are applied so as to cause a current to flow in the cell, wherein the amount of such current is indicative of the value of the data stored in the cell. The memory device includes appropriate circuitry to sense the resulting cell current in order to determine the data stored therein, which is then provided to data bus terminals of the device for access to other devices in a system in which the memory device is employed.
Flash memory is a type of electronic memory media which can be rewritten and hold its content without power. Flash memory devices generally have life spans from 100K to 10 MEG write cycles. Unlike dynamic random access memory (DRAM) and static random access memory (SRAM) memory chips, in which a single byte can be erased, flash memory is typically erased and written in fixed multi-bit blocks or sectors. Conventional flash memories are constructed in a cell structure wherein a single bit of information is stored in each flash memory cell. In such single bit memory architectures, each cell typically includes a MOS transistor structure having a source, a drain, and a channel in a substrate or P-well, as well as a stacked gate structure overlying the channel. The stacked gate may further include a thin gate dielectric layer (sometimes referred to as a tunnel oxide) formed on the surface of the P-well. The stacked gate also includes a polysilicon floating gate overlying the tunnel oxide and an interpoly dielectric layer overlying the floating gate. The interpoly dielectric layer is often a multilayer insulator such as an oxide-nitride-oxide (ONO) layer having two oxide layers sandwiching a nitride layer. Lastly, a polysilicon control gate overlies the interpoly dielectric layer.
The control gate is connected to a wordline associated with a row of such cells to form sectors of such cells in a typical NOR configuration. In addition, the drain regions of the cells are connected together by a conductive bitline. The channel of the cell conducts current between the source and the drain in accordance with an electric field developed in the channel by the stacked gate structure. In the NOR configuration, each drain terminal of the transistors within a single column is connected to the same bitline. In addition, each flash cell associated with a given bit line has its stacked gate terminal coupled to a different wordline, while all the flash cells in the array have their source terminals coupled to a common source terminal. In operation, individual flash cells are addressed via the respective bitline and wordline using peripheral decoder and control circuitry for programming (writing), reading or erasing functions.
Programming a flash memory cell is typically done by channel hot electron (CHE) by grounding the source region, applying a relatively high positive voltage to the control gate and applying a moderate voltage to the drain to generate high energy or hot electrons, which accumulate in the floating gate until the effective threshold voltage of the cell rises to a programmed threshold voltage, which is sufficient to inhibit current flow through the channel region during any subsequent read mode operation. Typically, in the read mode, a relatively low positive voltage is applied to the drain, a moderate voltage is applied to the control gate and the source is grounded. The magnitude of the resulting current can be sensed in order to ascertain whether the cell is programmed or erased.
Flash memory core cells are typically erased in blocks or sectors of many such cells. Negative gate erase operation involves providing a moderate positive voltage (e.g., 5V or VCC) to the source, floating the drain, grounding the substrate, and applying a negative voltage (e.g., −8 volts) to the gate. Subsequently, an erase verify operation is performed to ensure proper erasure of each of the core cells in the sector. Thereafter, soft programming is employed, wherein a small amount of charge is injected into the cell to rectify or mitigate over-erased conditions resulting from repeated erasure of the cell. The amount of charge injected during the soft programming is controlled so as not to over-program the cell, so that it passes erase verify even after a soft program verify operation, which is performed right after the soft programming operation.
During erase operations, negative voltages are applied to the gate of the core cell or cells of interest. The negative gate voltages are commonly applied using a regulated negative charge pump employing feedback to regulate the gate voltages. A voltage derived by dividing the output voltage of the pump is compared with a reference voltage, and the comparison is used to regulate the voltage applied to the cell gate. Capacitive voltage dividers are often used to divide the negative pump output voltage for such feedback purposes, wherein capacitive dividers utilize less power than resistive dividers. Metal capacitors have been previously employed in such capacitive regulator voltage divider applications. However, as semiconductor memory device densities increase, it is desirable to reduce the physical size of the components in the negative pump and associated regulation circuitry. Thus, it is desirable to provide methods and apparatus for providing negative gate voltages to core cells during erase operations, by which the size of the negative voltage circuitry can be reduced.